1. Field of the Invention
This invention is related to laminated multilayer circuit boards and the like and more particular to improvements in the fabrication thereof.
2. Description of the Prior Art
Various methods well known to those skilled in the art are used to produce laminated multilayer printed circuit boards.
One such prior art method is described, for example, in the publication entitled "High Resolution Circuitization Process", J. G. Cutillo et al, IBM.RTM. Technical Disclosure Bulletin, Vol. 20, No. 9, February 1978, pp. 3378-3379. For purposes of explanation and comparison with the present invention, this prior art method is described next with reference to the associated apparatus schematically represented in FIGS. 1A-1F and 4.
This prior art method begins with a thin conductive metal, e.g. copper, layer 1 or foil that has peelably adhered to its surface 1a a temporary carrier or support base 2 along the latter's outer surface 2a, FIG. 1A. Formation of the printed circuit pattern that is ultimately to become part of the laminate 6, FIG. 1F, is provided by an additive plating process which takes place on the other surface 1b of layer 1. More particularly, after applying to the surface 1b, a layer 3 of an appropriate photoresist and predetermined type, e.g. negative, layer 3 is exposed and developed with the desired circuit pattern using well known photolithographic techniques. For sake of clarity layer 3 is shown in phantom outline in FIG. 1A. The unexposed regions of layer 3 are removed leaving openings 3a in the remaining, i.e. exposed, regions 3b of layer 3 as shown in FIG. 1B. Next, conductive circuit members, e.g. lines 4, are additively plated to surface 1b through the openings 3a resulting in the deposition of the desired circuit pattern on surface 1b. Next, the photoresist regions 3b are removed by an appropriate chemical stripping process resulting in the structure of FIG. 1C.
One or more stacked sheets, not shown, of an uncured epoxy fiber-glass are then juxtaposed on top of the conductive lines 4 of the structure of FIG. 1C and subjected to an appropriate curing process. As a result of the curing process, the sheets are coalesced into an integral layer 5 which forms on top of the exposed regions, i.e those regions not plated to by the lines 4, of the surface 1b of layer 1 and around the sides and top of the lines 4 thereby embedding the conductive lines 4 in the layer 5 except for the conductor surfaces 4a, cf. FIG. 1D. Thus, surfaces 4a are flush mounted with the surface 5a of layer 5. Next, base member 2 is peeled away from the surface 1a of layer 1, as shown in FIG. 1E.
Thereafter, layer 1 is removed by a flash etchant from surface 5a leaving a laminate 6 with the conductive lines 4 flush mounted, i.e. with the surfaces 4a thereof flush mounted with the surface 5a as aforedescribed and shown in FIG. 1F. Laminate 6 is now ready to be appropriately stacked with one or more other dielectric laminates whereupon the stack is subjected to a laminating process. The laminating process coalesces the individual laminates and more particularly the individual dielectric layers thereof into an integral, i.e. monolithic, laminated multilayer printed circuit board in a manner well known to those skilled in the art.
Heretofore, the laminated multilayer printed circuit boards fabricated with the aforedescribed prior art method were susceptible to delaminating and hence were unreliable and/or defective. The delamination was the result of the poor adhesion effected between the surface 4a of the conductive lines 4 to the dielectric layer of the adjacent laminate and/or the poor adhesion between respective dielectric layers of adjacent laminates. Moreover, with the advent of high density conductor laminates, the problem becomes even more acute.
Heretofore, in most of the prior art of which I am aware, the aforedescribed lamination problem is either not addressed or, if addressed, the solution thereof is not amenable for implementation into the aforedescribed method without a partial or complete change thereof thereby adding to the complexity and/or expense of the basic method. Examples of the prior art in which the lamination problem is not addressed are as follows, to wit: U.S. Pat. Nos. 2,692,190; 3,152,938; 3,324,014; 3,791,858; 3,998,601; U.S. Pat. No. Re. 29,820; the publications appearing in the IBM.RTM. Technical Disclosure Bulletin, viz., "Flush Printed Circuits", E. D. Miles, Vol. 1, No. 2, August 1958, p. 25, "Mechanically Bonded Printed Circuit", M. M. Haddad et al, Vol. 2, No. 1, June 1959, p. 9, "Multilayer Laminated Circuit Construction", M. M. Haddad, Vol. 7, No. 2, July 1964, pp. 154-155, "Flush Molding Of Printed Circuitry", E. J. Webb et al, Vol. 8, No. 8, January 1966, pp. 1025-1026, "Additive Multilayer Circuit" M. M. Haddad, Vol. 8, No. 11, April 1966, p. 1482, "Molded Printed Circuits", X. Kollmeier et al, Vol. 9, No. 11, April 1967, pp. 1520-1521, "Multilayer Circuit Fabrication", A. E. Peter et al, Vol. 10, No. 4, September 1967, pp. 359-360, and the aforementioned "High Resolution Circuitization Process", J. G. Cutillo, Vol. 20, No. 9, February 1978, pp. 3389-3390; and the publication entitled "Other Forms, Variations of Well-Known Techniques Designed For Printed-Wiring Reliability", Electronic Design. The inventive method of the present invention overcomes the aforementioned problems in a more reliable and less expensive manner as will become apparent from the description hereinafter.